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Computer Architecture

The prospects for 128 bit processors (John R. Mashey) [8913 bytes]
64 bit processors: history and rationale (John R. Mashey) [32401 bytes]
AMD64 (Linus Torvalds; Terje Mathisen) [12514 bytes]
Asynchronous logic (Mitch Alsup) [3766 bytes]
Atomic transactions (Mitch Alsup; Terje Mathisen) [86188 bytes]
BCD instructions: RISC and CISC (John R. Mashey) [3624 bytes]
Big Data (John R. Mashey, Larry McVoy) [30027 bytes]
Byte_addressing (John R. Mashey) [2819 bytes]
Caches (John R. Mashey; John D. McCalpin) [7821 bytes]
Parity and ECC use in caches (John R. Mashey) [1549 bytes]
Cache thrashing (Andy Glew; Linus Torvalds; Terje Mathisen) [9422 bytes]
Carry bits; The Architect’s Trap (John R. Mashey) [8038 bytes]
CMOS logic speeds (Mitch Alsup) [9317 bytes]
CMOV (Terje Mathisen) [2341 bytes]
CPU feature economics (John R. Mashey) [3860 bytes]
CPU power usage (Mitch Alsup) [2795 bytes]
Hardware to aid debugging (John R. Mashey) [10408 bytes]
DRAM cache (Mitch Alsup; Terje Mathisen) [8807 bytes]
DRAM latencies (Mitch Alsup) [3056 bytes]
Endian (John R. Mashey) [2053 bytes]
Separate floating point


 

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