The silicon foundry business is heating up, as vendors continue to ramp their 16nm/14nm finFET processes. At the same time, they are racing each other to ship the next technologies on the roadmap—10nm and 7nm.
But the landscape is complicated, with each vendor taking a different strategy. Samsung, for one, plans to ship its 10nm finFET technology by year’s end. The company will focus on 10nm for now, although it also is working on 7nm in R&D.
In contrast, TSMC will move into 10nm production in early 2017, with 7nm slated to ship in 2018. TSMC sees 10nm as a shorter node and is emphasizing 7nm.
Meanwhile, Intel will move into 10nm production by mid-2017, with 7nm slated for 2018 or 2019, sources said. In addition, GlobalFoundries will also be in the mix at 7nm.
Based on those schedules and other factors, foundry customers that can afford to migrate to these advanced nodes face some tough decisions. Initially, customers may ask themselves a fundamental question: Does it makes more sense to migrate to either 10nm or 7nm. Or should they do both?
Over time, OEMs will embrace both 10nm and 7nm chips. But most foundry customers don’t have the resources to pursue both technologies, so they must weigh their options and make the right choices. Here are the main avenues for customers:
• Migrate from 16nm/14nm to 10nm.
• Skip 10nm and move directly to 7nm.
• Do both 10nm and 7nm.
• Stay at 16nm/14nm.
Another idea is to consider 2.5D stacked die or fan-out packaging.
The permutations are also complex for those at 28nm. If 28nm customers can afford it, they may move to 16nm/14nm and perhaps beyond. 22nm FD-SOI is another option. And, of course, if they can’t afford to migrate, they will stay put.
“This is going to be an interesting fork in the road for many customers,” said Kelvin Low, senior director of foundry marketing at Samsung Semiconductor. “There are some companies, particularly large companies, that will use every single node that the foundries introduce. The majority are kind of stepping back and evaluating whether that is the right recipe for success. We are starting to see a lot of small- to medium-size vendors skipping nodes today.”
For leading-edge foundry customers, it’s a complex decision to go with 10nm and/or 7nm. For example, both 10nm and 7nm are based on scaled down versions of today’s finFET transistors. But the definitions of these nodes are fuzzy, and not all 10nm and 7nm technologies are alike.
In theory, 7nm provide better performance than 10nm. But 10nm is expected to ship much sooner than 7nm.
Indeed, there are a multitude of tradeoffs. Cost, of course, is a big factor. “Everything is usually driven by economics,” said Matt Paggi, vice president of advanced technology at GlobalFoundries.
In fact, it costs $271 million to design a 7nm system-on-a-chip, which is about nine times the cost to design a 28nm device, according to Gartner. “Not that many people can afford to (design chips at 10nm and 7nm) unless they have a high-volume runner and can see a return-on-investment,” said Samuel Wang, an analyst with Gartner.
It’s also too expensive to make the wrong choice at 10nm and 7nm. Making the wrong bet can be disastrous.
To help foundry customers get ahead of the curve, Semiconductor Engineering has taken a look at the various tradeoffs at 10nm and 7nm.
Not long ago, it was a straightforward and inexpensive effort to migrate from one node to another. But the dynamics appeared to change at 16nm/14nm, when foundry vendors introduced finFET transistors for leading-edge designs.
FinFETs solve the short-channel effects that plague leading-edge planar devices. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.
While finFETs keep the industry on the scaling path, the problem is that fewer and fewer foundry customers can afford the technology. In total, the average IC design cost for a 14nm chip is about $80 million, compared to $30 million for a 28nm planar device, according to Gartner.
For most, 28nm is suitable for many applications. “28nm will be a sweet spot for a long time, especially for cost and the ability to have the right power performance,” Samsung’s Low said.
Still, there is a sizable customer base that will migrate to 16nm/14nm and beyond. But in the early stages of 16nm/14nm, foundry vendors struggled with their yields. IC designers wrestled with the double patterning issues at that node.
Recently, though, the 16nm/14nm yields have improved. “Right now, there is less concern about the uncertainties of double patterning,” Low said. “All of that has gone away.”
Today, 16nm/14nm processes are more mature, which is fueling a broader adoption of the technology. “We are observing that 14nm could become a long node,” Low said. “There are not only the mobile and consumer guys that are enjoying the benefits of 14nm finFETs, but networking and server customers, as well.”
Amid the 16nm/14nm ramp, foundries are now pushing 10nm and 7nm. But needless to say, customers face some daunting challenges at those nodes. For one thing, there is some confusion between 10nm and 7nm.
“Not all 10nm technologies are the same,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel. “It’s now becoming clear that what other companies call a ‘10nm’ technology will not be as dense as Intel’s 10nm technology. We expect that what others call ‘7nm’ will be close to Intel’s 10nm technology for density.”
It wasn’t always like that. Traditionally, chipmakers scaled the key transistor specs by 0.7X at each node. This, in turn, roughly doubles the transistor density at each node.
Intel continues to follow this formula. At 16nm/14nm, though, others deviated from the equation from a density standpoint. For example, foundry vendors introduced finFETs at 16nm/14nm, but it incorporated a 20nm interconnect scheme.
Technically, the foundries didn’t introduce finFETs at a full node (14nm), but rather at a half node. TSMC, for one, calls it 16nm.
Still, foundries found a way to provide value to their customers at 16nm/14nm. “Foundries are less fixed on sticking to a 0.7X pitch shrink per node and more on providing their customers with some combination of power, performance, area and cost benefit at a half-node cadence,” said Mike Chudzik, senior director of strategic planning at Applied Materials.
There are other deviations from the roadmap. For example, the complexity of the technology is causing the cadence of the nodes to extend from their historical two-year patterns to roughly 2.5 years, analysts said.
With those issues in mind, customers must sort out the tradeoffs between the various foundry vendors at 10nm and 7nm. As before, they will look at the traditional metrics—performance, power, area scaling, schedule, and cost (PPASC).
The decision to select one process over another also depends on the product requirements. “Each process has different tradeoffs,” said Mark Liu, president and co-CEO of TSMC. “It also depends on the timing of the process.”
For many, it comes down to cost. For a 10nm chip, it takes $120 million for the design cost, plus 60% for the embedded software. In comparison, the total design cost is roughly $271 million for a 7nm chip, according to Gartner.
“It will take chip designers about 500 man-years to bring out a mid-range 7nm SoC to production,” Gartner’s Wang said. Therefore, a team of 50 engineers will need 10 years to complete the chip design to tape-out. In comparison, it could take 300 engineer-years to bring out a 10nm device, 200 for 14nm, and 100 for 28nm, according to Gartner.
Beside cost, there is other trouble on the horizon—the PPASC equation breaks down at 10nm and 7nm. “Because Moore’s Law has broken down and you no longer get gains in all areas at the same time by going to the next node, each foundry customer will have a different strategy, depending on which parameter is most important,” according to a source at one large customer, who asked not to be named.
Generally, customers could go down one of two paths for 10nm and 7nm, the source said. The first path is based on a combination of power and performance. The second is based on cost.
The power/performance path is for customers that will migrate directly from 16nm/14nm to 10nm. These customers require a new chip at each node in response to products with rapid design cycles, such as smartphones and PCs. This group includes suppliers of microprocessors and applications processors. Apple, Intel, Mediatek, Qualcomm and Samsung fall into this crowd.
Then, there is the cost-driven decision. This is for foundry customers who may have lower volume products. They may not recoup their investment at 10nm. So, it makes more sense for them to skip 10nm and move to 7nm.
Some FPGA vendors fall in this camp. IDMs and foundry customers that developed 10nm would also move to 7nm.
There is another way to look at the various scenarios. “This is going to be exactly the same thing as 20nm. 20nm was a transition node. It only served a few customers,” Gartner’s Wang said.
“10nm will be the same thing as 20nm. Customers who used 20nm before will most likely use 10nm,” Wang said. “Customers that skipped 20nm, and went directly to 16nm, will most likely do the same thing. They will skip 10nm and go to 7nm.”
All told, IDMs and foundry customers will simultaneously ship chips at several different nodes. “Chipmakers targeting different applications and serving different markets will have varying strategies in adopting these leading-edge nodes,” said Yang Pan, chief technology officer for the Global Products Group at Lam Research.
“10nm is expected to start ramping within the next 12 months, and 7nm development is progressing at full speed,” Pan said. “With rising development costs and the increasing cost to migrate designs from one node to the next, we anticipate more overlap between nodes as the industry tries to maximize returns from investments made at each node. Chipmakers targeting different applications and serving different markets will have varying strategies in adopting these leading-edge nodes.”
What is 10nm?
Still, the decisions aren’t quite that simple. In fact, there are two schools of thought at 10nm and 7nm. One camp says that 10nm will be a robust node, while others say 7nm will become the more dominate node.
Samsung is in the first camp. “We see 10nm as a very healthy node. It’s probably going to be widely adopted. It has the right PPASC,” Samsung’s Low said. “We don’t see a need to rush into 7nm. 7nm has to be properly defined, taking cost into account.”
According to officials from Samsung, 193nm immersion lithography and multi-patterning will extend to at least 10nm. With those patterning technologies in place, foundry customers and IDMs can develop cost-effective IC designs at 10nm.
But at 7nm, optical and multi-patterning are simply too complex and expensive, at least according to Samsung. So to make 7nm cost effective, it makes more sense to wait for EUV. In theory, EUV can simplify the patterning process.
“EUV has been delayed for a long time. During that time, 193nm immersion has been the workhorse for the semiconductor industry,” added Seong-Sue Kim, a technical staff member within the Semiconductor R&D Center at Samsung. “But in the case of 7nm, the situation is different. Of course, 193nm immersion has (advanced) technologically, but the problem is cost. The situation is we need EUV.”
TSMC, however, has a different strategy. “(TSMC) is also aggressive in terms of expanding into 10nm,” Gartner’s Wang said, “but 10nm is not considered as a main technology by TSMC. They actually are pushing hard on 7nm.”
Foundry vendors, meanwhile, are keeping their 10nm specs close to the vest. In general, a 10nm finFET would include the usual features, such as copper interconnects and high-k/metal-gate. It would make use of 193nm immersion and multiple patterning.
As it stands today, 10nm will ship by year’s end, roughly a year ahead of 7nm. 10nm has a 22% speed improvement over 16nm/14nm.
There are some disadvantages with 10nm, though. “I believe a few key customers looked at the 10nm process offering from TSMC and decided it will be better to wait for the 7nm solution,” said Joanne Itow, an analyst with Semico Research. “10nm will not get enough improvement compared to all the time and money required.”
There are other tradeoffs. TSMC is moving from a 2D layout scheme at 16nm to 1D technology at 10nm. 1D layouts are easier to make in the fab, but they involve more restrictive design rules.
Others may follow the 2D layout path at 10nm. This technology is harder to make in the fab, but it enables a more flexible design environment.
“Up through 16nm, all the foundry approaches to multi-patterning have been very similar,” said David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics. “Beginning with 10nm, those approaches have diverged.
Correspondingly, the specific types of checks, coloring requirements, error visualization and design considerations are different between them.”
What is 7nm?
Like 10nm, 7nm has some pluses and minuses. Compared to 16nm/14nm, 7nm provides a 35% speed improvement, 65% less power, and a 3.3X density improvement, according to Gartner.
Based on PPASC metrics and the cost-per-transistor curve, 7nm looks like a better option, at least according to some. “In general, we are seeing that this financial equation is pretty tight for most customers at 10nm,” GlobalFoundries’ Paggi said. “7nm, for most customers in most of the markets, appears to be a more favorable financial equation.”
There is room for 10nm, at least for some applications. “But for the largest part of the market, we see that the economics of 7nm is compelling enough,” Paggi said. “And at 10nm, it’s marginal.
“(7nm) brings a lot larger economic benefits,” he said. “In most cases, that outweighs the design cost you would have to spend. There are power advantages as well as a longer battery life.”
Still, 7nm presents some major challenges. Like 10nm, 7nm is a scaled version of a finFET. Originally, chipmakers hoped to insert extreme ultraviolet (EUV) lithography at 7nm. But it’s unlikely EUV will intersect the early part of 7nm, meaning that chipmakers must use complex multiple patterning schemes at that node.
What will this all mean for IC designers at both 10nm and 7nm? “These nodes first introduce constraints and checking for triple, quad litho-etch based and self-aligned double-patterning based processes,” Mentor’s Abercrombie said. “So designers will need to learn these new concepts and checks associated with them. In addition, there is a general trend to more constrained layouts. There is a general move towards track and grid based layout forms. Expect this trend to increase moving forward.”
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